Please use this identifier to cite or link to this item: http://library.ediindia.ac.in:8181/xmlui//handle/123456789/9722
Title: Development of FPGA and DDR Memory Based Fast Event Recording and Data Storage System for Machine Vision Applications
Authors: Patel, Jinal
Chaudhari, Vishnu
Ganeshan, Navin
Joshi, H C
Keywords: Field programmable gate array
Double data rate -SDRAM
Event monitoring
Interlock
Machine vision
Issue Date: 6-Jun-2019
Publisher: Emerald Group Publishing
Abstract: For fail-safe operation of any plant, machine, or scientific experiment, the real-time monitoring of every component is essentially critical. Lossless acquisition of raw data, signal processing, and data storage are the main electronic processes for the monitoring of machine. The recording and storage of fast events demand high speed embedded system with higher storage capacity and speed. The field programmable gate array (FPGA) is a reconfigurable processor available to work at high speed ~500 MHz with signal processing and computer interfacing features. The double data rate (DDR) memory is available with 1 G bits capacity and speed of ~500 Mbps. In this paper, we report the development of FPGA-based event recording system for monitoring of glass window fabricated for one of the vacuum chambers. The glass window may get damaged with time due to high power laser and surroundings. The FPGA and DDR memory based embedded systems perform routine checks on the glass window and provide the mechanism for on-board data storage and send status in real time to other sub-systems during false events for operating the machine interlock. Details of hardware architecture, software development, and results are presented in the paper. We believe that the developed work will be useful implications in many industrial and research applications.
URI: http://library.ediindia.ac.in:8181/xmlui//handle/123456789/9722
ISBN: 9781786354273
Appears in Collections:Design Thinking/Prototype Testing

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