Design and Implementation of Packet Routing Algorithm with Packet Error detection Logic for NOC and Verification in System Verilog

Abstract

Network on chip (NoC) is one of the proficient on-chip correspondence design for system on chip (SoC) where an extensive number of computational and capacity blocks are incorporated on a single chip. NoCs have handled the inconveniences of SoCs just as they are adaptable. Variable on-chip communication is basic for exploiting stupendous processing power obtainable on a multi-center chip. Routing algorithms assume a genuine job for the communication quality and execution of the on-chip interconnection systems. NoC to decouple communication from computations. Router is a spine of NoC, consequently, proficient plan of router is basic to improve the execution of the system. In the present work, we focus on router input-output convention (protocol) structure. Proposed framework incorporates virtual slice through instrument for close loop communication. Router 1×3 has single information port and three output ports. Top-level architecture designed with sub-modules like FIFO, FSM, synchronizer, and register utilize Verilog language. Router RTL designed analyzed and verified utilizing Xilinx 14.7 Artix-7- XC7A100T FPGA family. Coverage is an estimation to survey the progression of useful check development. This expects a main work to obtain a sensible image on how well the structure has been confirmed. Code coverage is a fundamental coverage variety which is gathered consequently. It uncovers to you how well your Verilog code has been practiced by your testbench. Design and verify the functionality of the “packet algorithm with packet error detection logic for NOC”. We will implement class-based layer testbench with constraint random verification and coveragedriven verification.